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? semiconductor MSC1200-01/1200v-01 1/26 fedl1200v-03 ? semiconductor MSC1200-01/1200v-01 30-bit duplex controller/driver with digital/analog dimming and keyscan functions general description the MSC1200-01/1200v-01 is a bi-cmos display driver for 1/2-duty vacuum fluorescent display tube. this device consists of a 64-bit shift register, latches, an analog dimming circuit, a digital dimming circuit, a keyscan circuit, and drivers. the interface with a microcomputer can be done only with four signal lines (cs, data i/o, clock, and int). also, the data i/o and clock signal lines can be shared with other peripherals by using the chip select function. features ? power supply voltage : 8v to 18v (built-in 5v regulator for logic) ? operating temperature range : C40 c to +85 c ? 30-segment driver outputs (i oh = C6ma at v oh = v dd C 0.8v) ? built-in analog dimming circuit (pwm: 12.5% max at 6-bit resolution) ? built-in digital dimming circuit (11-bit resolution) ? built-in 5 x 6 keyscan circuit ? built-in rc oscillation circuit (external r and c) ? built-in power-on-reset circuit. ? the product name differs depending on the bonding option pin selected: pwm out/ blank in : MSC1200-01 data out : msc1200v-01 ? package : 56-pin plastic qfp (qfp56CpC910-0.65C2k) (product name: MSC1200-01gs-2k/msc1200v-01gs-2k) fedl1200v-03 this version: sep. 2000 previous version: nov. 1997
? semiconductor MSC1200-01/1200v-01 2/26 fedl1200v-03 block diagram seg1 v dd gnd test1 osc0 osc1 v park v dim cs datai/o clock 5v por seg30 grid1 grid2 data out (optional) pwm out/ blank in (optional) int r r r r s2, s7, s3, s8 sa s9 s4 s5, s6, s9 1 03 25 41 03 24 row column r s1, s6, s7, s8 d ck r/c osc timing generator analog dimming digital dimming 5 6 keyscan circuit selector 64-bit shift register m3 m2 m1 m0 sa s9 s8 s7 s6 s5 s4 s3 s2 s1 bit latch mode selector multiplexer pla (32 32 matrix) 30 segment drivers grid driver control circuit 5v regulator &por
? semiconductor MSC1200-01/1200v-01 3/26 fedl1200v-03 input and output configuration ? schematic diagrams of logic portion input circuit ? schematic diagrams of logic portion input circuit 2 ? schematic diagrams of logic portion input/ output circuit ? schematic diagrams of logic portion output circuit ? schematic diagrams of driver output circuit gnd v dd gnd input (5v reg.) gnd (5v reg.) v dd gnd col n test1 gnd (5v reg.) v dd gnd datai/o gnd (5v reg.) gnd gnd (5v reg.) gnd output (5v reg.) gnd v dd gnd output v dd
? semiconductor MSC1200-01/1200v-01 4/26 fedl1200v-03 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 v dd v park v dim cs clock data i/o int test1 *1 column0 column1 column2 column3 column4 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 column5 row0 row1 row2 row3 row4 gnd osc0 osc1 seg1 seg2 seg3 seg4 seg5 grid2 grid1 seg30 seg29 seg28 seg27 seg26 gnd seg25 seg24 seg23 seg22 seg21 seg20 56-pin plastic qfp *1 bonding option pin (data out or pwm out/ blank in )
? semiconductor MSC1200-01/1200v-01 5/26 fedl1200v-03 pin descriptions pin symbol description 1v dd power supply 2v park day/night switching pin. when the high level is input, the ic enters the night mode and the value determined by the analog or digital dimming circuit is used as the output duty. when the low level is input, the ic enters the day mode and the output duty is about 100%. analog voltage input for determining the analog dimming value. when the analog dimming circuit is used, the output duty is determined by the analog voltage to be input to this pin. when only the digital dimming circuit is used, pull down this pin to gnd. 3v dim chip select input. only when the high level is input to this pin, interfacing with a microcomputer is available through "clock" and "data i/o" pins. therefore, 2 signal lines of "clock" and "data i/o" can be shared with other peripherals. 4cs serial clock input. data is input-output through "data i/o" pin at the rising edge of the serial clock. 5 clock serial data input-output. this pin enters output mode only when the keyscan mode is selected. it enters input mode when other mode is selected. 6 data i/o interrupt signal output to microcomputer. when any key is pressed or released, key scanning is started. after the completion of the one cycle, this pin goes to the high level and keeps the high level until keyscan stop mode is selected. 7 int test signal input. as this pin has a built-in pull-up resistor, it must be left open or pulled up in the normal operation mode. when the low level is input to this pin, seg1-30 go to the high level, and grid1 and grid2 go to the low level. (all segments go on.) 8 test1 serial data output. selecting this pin specifies the msc1200v-01. the data from data i/o is shifted out on the rising edge of the shift clock with a delay of 64 bits in the shift register. this pin can be used for connecting the ic with a led driver in series. 9 data out (option) when the v park pin is at the high level, the pulse with the duty ratio determin- ed by the analog or digital dimming circuit is output through this pin. when this pin is at the low level, the pulse with the duty ratio determined by external circuit is input to this pin. this pin has an internal active pull-up resistor, which becomes active only when the v park pin is at the low level. when the v park pin is at the low level, this pin receives blanking signal from external circuits, so that output duty cycle can be controlled. selecting this pin speci- fies the MSC1200-01. type i i i i i/o o i o 9 pwm out/ blank in (option) i/o
? semiconductor MSC1200-01/1200v-01 6/26 fedl1200v-03 pin symbol description 21, 49 gnd ground 22, 23 osc0 osc1 connecting pins for rc oscillation circuit. connect a resistor between osc1 and osc0, and a capacitor between osc0 and ground. 24-48, 50-54 seg1-30 segment signal output. signals for driving vf display tube are output through these pins. 55, 56 grid1,2 grid signal output. signals for driving vf display tube are output through these pins. signals inverted with respect to grid signals are output. normally, these pins are connected to the external grid driver (pnp transistor etc.) inputs. type i/o o o return inputs from key matrix switch. a pull-up resistor is internally connected to each of these pins so that they are at the high level except when the low level is input by depression of a key. these pins are "l" active. key switch scanning outputs. normally the low level is output through these pins. when any key is depressed or released, keyscanning is started and is continued until keyscan stop mode is selected. when the keyscan stop mode is selected and then keyscanning is stopped, all outputs of row0-4 go back to the low level. o i row0-4 column 0-5 16-20 10-15
? semiconductor MSC1200-01/1200v-01 7/26 fedl1200v-03 absolute maximum ratings parameter symbol condition rating unit supply voltage v dd C0.3 to +20 v all inputs except v park input voltage (1) v in1 C0.3 to +6 v v park input voltage (2) v in2 C0.3 to v dd +0.3 v storage temperature t stg C65 to +150 c ta = 85 c power dissipation p d 400 mw recommended operating conditions parameter symbol condition max. unit supply voltage v dd 18 v typ. all inputs except v park & osc0 high level input voltage (1) v ih1 5.5 v min. 8 3.8 v park high level input voltage (2) v ih2 v dd v 3.8 osc0 high level input voltage (3) v ih3 5.5 v 4.5 all inputs except osc0 low level input voltage (1) v il1 0.8 v 0 osc0 low level input voltage (2) v il2 0.5 v 0 clock frequency f c 250 khz r = 4.7k w , c=10pf osc frequency f osc mhz 3.3 f osc =3mhz frame frequency f fr hz 201 operating temperature t op +85 c C40
? semiconductor MSC1200-01/1200v-01 8/26 fedl1200v-03 electrical characteristics dc characteristics parameter symbol condition max. unit high level input voltage (1) v ih1 5.5 v min. 3.8 (ta = C40 to +85 c, v dd = 8 to 18v) high level input voltage (2) v ih2 v dd v 3.8 high level input voltage (3) v ih3 5.5 v 4.5 low level input voltage (1) v il1 0.8 v 0 low level input voltage (2) v il2 0.5 v 0 v ih1 = 5.0v high level input current (1) i ih1 5 m a C5 v ih2 = 5.0v high level input current (2) i ih2 30 m a C30 v ih3 = 5.0v high level input current (3) i ih3 80 m a C80 v il1 = 0v low level input current (1) i il1 C5 m a C5 v il2 = 0v low level input current (2) i il2 C15 m a C160 v il3 = 0v low level input current (3) i il3 0.1 ma C0.6 v i = 0 to 5.5v input leakage current i il 10 m a C10 v dd = 9.5v, i oh1 = C6ma high level output voltage (1) v oh1 v v dd C0.8 high level output voltage (2) f osc = 3.3mhz, no load i dd 20 ma power supply current v dd = 9.5v, i oh2 = C200 m a v oh2-1 6v 4 v dd = 9.5v, output open v oh2-2 6v 4.5 v dd = 9.5v, i ol1-1 = 500 m a v ol1-1 2v v dd = 9.5v, i ol1-2 = 200 m a v ol1-2 1v v dd = 9.5v, i ol1-3 = 2 m a v ol1-3 0.3 v v dd = 9.5v, i ol2 = 200 m a v ol2 0.8 v low level output voltage (1) low level output voltage (2) *1 *9 *2 *10 *2 *3 *4 *5 *3 *4 *5 *6 *7 *8 *7 *8 *1 applicable to all input pins (except v park and osc0 pins) *2 applicable to osc0 pin *3 applicable to clock, data i/o, cs, and v park pins *4 applicable to column0 to column5 and pwm out/ blank in pins *5 applicable to test1 pin *6 applicable to v dim pin *7 applicable to seg1 to seg30, grid1 , and grid2 pins *8 applicable to row0 to row4, data i/o, pwmout/ blank in , dataout, and int pins. *9 applicable to v park pin *10 applicable to all input pins (except osc0)
? semiconductor MSC1200-01/1200v-01 9/26 fedl1200v-03 ac characteristics parameter symbol condition max. unit r = 4.7k w 1%, c = 10pf 5% oscillation frequency f osc 4.66 mhz min. 2 (ta = C40 to +85 c, v dd = 8 to 18v) clock frequency f c 250 khz clock pulse width t cw m s 1.3 data setup time t ds m s 1 data hold time t dh ns 200 cs pulse width t csw m s 68 cs off time t csl m s 30 cs setup time cs C clock time t csh m s 2 cs hold time clock C cs time t csh m s 2 data output delay clock C data output time t pd 1 m s ci = 100pf seg & grid output delay from cs t ods 8 m s ci = 100pf, t = 20% to 80% or 80% to 20% of v dd slew rate (all drivers) t r 5 m s input frequency to osc0 from outside external input only f osci 3.7 mhz 2.4 cs time at power-on t pcs m s 300 when mounted on the unit v dd =0.0v hold time at power-off t pof ms 5 when mounted on the unit rise time at power-on t prz 100 m s pwm out frequency f pwm 568 hz 244 frame frequency f fr 284 hz 122
? semiconductor MSC1200-01/1200v-01 10/26 fedl1200v-03 dimming characteristics ? dc characteristics parameter condition max. unit d/a output voltage error 3% typ. (ta = C40 to +85 c, v dd = 8 to 18v) note 1 reference voltage accuracy 6% min. note: 1. reference voltage is 6.6v typical. keyscan characteristics parameter condition max. unit f osc =3.3 mhz keyscan cycle time 640 m s typ. 390 (ta = C40 to +85 c, v dd = 8 to 18v) f osc =3.3 mhz keyscan pulse width 128 m s 78 min. 275 55
? semiconductor MSC1200-01/1200v-01 11/26 fedl1200v-03 timing diagram figure 1 data input timing figure 2 data output timing t csw t csl t csh f c t css t cw t cw t ds t dh t dh t ds 0.8v 3.8v 0.8v 3.8v 0.8v 3.8v valid valid data i/o (input) clock cs data i/o (output) data out clock cs 0.8v 3.8v 0.8v 3.8v 0.8v 3.8v t css t csh t pd t pd
? semiconductor MSC1200-01/1200v-01 12/26 fedl1200v-03 timing diagram (continued) figure 3 power-on timing figure 4 seg & grid output timing 3.8v 8v t pcs cs v dd t pof t prz 0v t csw t ods t r t ods t r 3.8v 80% 20% cs seg1-30 g rid1, 2
? semiconductor MSC1200-01/1200v-01 13/26 fedl1200v-03 functional description power-on reset the ic is initialized by the built-in power-on reset circuit at power-on. the status of the internal circuit after initialization is as follows; 1) shift registers and latches are reset. 2) analog dimming is selected. 3) digital dimming data register is reset. 4) display data inp ut mode is selected. data input data input is valid only when the high level is applied to the "cs" pin. input data is input into the shift register through "data i/o" pin at the rising edge of clock. the data is automatically loaded to latches at the falling edge of "cs" signal. [data format] 1) display data input mode input data : 64 bits vf display data : 60 bits mode select data : 4 bits 2) correspondence between segment outputs and shift register bits 64 d59 63 d58 62 d57 53 d48 52 m3 51 m2 50 m1 49 m0 48 d47 3 d2 2 d1 1 d0 display data (12 bits) mode data (4 bits) display data (48 bits) bit first in ... ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 segn 302928272625242322212019181716151413121110987654321 grid1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 grid2 bit
? semiconductor MSC1200-01/1200v-01 14/26 fedl1200v-03 3) digital dimming data input mode input data : 16 bits digital dimming data : 11 bits mode select data : 4 bits 64 bit first in xx 63 11 62 10 61 9 60 8 59 7 58 6 57 5 56 4 55 3 54 2 53 1 52 m 3 51 m 2 50 m 1 49 m 0 msb lsb dimming data mode data x00000000000 duty cycle 0/2048 x00000000001 1/2048 x11111110000 2032/2048 x11111111111 2032/2048 input data (lsb) (msb)
? semiconductor MSC1200-01/1200v-01 15/26 fedl1200v-03 4) function mode m3 function s1 m2 m1 m0 0 display data input 000 s2 0 analog dimming select 011 s3 0 digital dimming select 101 s4 0 digital dimming data input & digital dimming select 001 s5 0 keyscan data output 111 s6 0 display data input & keyscan data output 110 s7 0 display data input & analog dimming select 010 s8 0 display data input & digital dimming select 100 s9 1 keyscan data output & keyscan stop 000 sa 1 keyscan s top 001 mode note: other combinations are used for test modes. 5) analog dimming mode analog dimming is automatically selected when the v park pin is set to the high level after power-on. therefore, when digital dimming is used, mode setting is required before the v park pin is set to the high level. the output duty ratio for analog dimming is 12.5% maximum. the correspondence between threshold voltage and output duty ratio is shown in v din threshold dimming voltage vs. pwm duty cycle.
? semiconductor MSC1200-01/1200v-01 16/26 fedl1200v-03 keyscan keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. then, keyscanning is continued until the keyscan stop mode signal is sent from a microcomputer. the int pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the int pin can be used as an interrupt signal. [keyscan timing] 1 cycle int row 4 row 3 row 2 row 1 row 0 depress/release keyscan stop mode is selected. note: keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. to stop keyscanning, it is required to select the keyscan stop mode once again.
? semiconductor MSC1200-01/1200v-01 17/26 fedl1200v-03 [example] a) when key input status is changed keyscan keyscan int cs keyscan stop keyscan data output keyscan stop keyscan data output depress release keyscan stop keyscan stop sa s5 s5 sa keyscan keyscan int cs keyscan stop keyscan data output keyscan stop keyscan data output depress release * 1 keyscan stop sa s5 sa s5 b) when key input status is changed before keyscan stop mode select *1: keyscanning resumes after short period of keyscan stop.
? semiconductor MSC1200-01/1200v-01 18/26 fedl1200v-03 keyscan data output when keyscan data output mode is selected, "data i/o" pin is changed to an output mode. then, 30 bits of keyscan data come out from "data i/o" pin synchronizing with the rising edge of the clock. after the completion of 30 bits data output, the ic returns to the display data input mode synchronizing with the falling edge of cs. [data format] 1) keyscan data stop mode since the data i/o pin goes to the output mode after the keyscan stop mode signal is received, be sure to output the keyscan data. input data : 16 bits mode select data : 4 bits 64 bit first in xx 63 xx 62 xx 61 xx 60 xx 59 xx 58 xx 57 xx 56 xx 55 xx 54 xx 53 xx 52 m 3 51 m 2 50 m 1 49 m 0 mode data 2) keyscan data output mode input data : 30 bits output data : 30 bits 30 clock first out s 45 29 s 44 28 s 43 ..... ..... 9 s 12 8 s 11 7 s 10 6 s 05 5 s 04 4 s 03 3 s 02 2 s 01 1 s 00 keyscan data sxx -- row column 3) key switch matrix for column input and row output s 00 s 01 s 02 s 03 s 04 s 05 s 10 s 11 s 12 s 13 s 14 s 15 s 20 s 21 s 22 s 23 s 24 s 25 s 30 s 31 s 32 s 33 s 34 s 35 s 40 s 41 s 42 s 43 s 44 s 45 column 0 column 1 column 2 column 3 column 4 column 5 = row0 row1 row2 row3 row4
? semiconductor MSC1200-01/1200v-01 19/26 fedl1200v-03 grid/seg driver operation and digital/analog dimming operation figure 5 shows the output timing of the grid and seg driver when the v park is the "h" level. figure 6 shows the output timing of the grid and seg drivers for the digital diming mode operation. figure 7 shows the output timing of the grid and seg drivers for the analog dimming mode operation. grid1 16 bit times 6 bit times 2032 bit times 2038 bit times 10 bit times 1 frame 4096 bit times grid2 seg1-30 figure 5 grid and seg output timing (v park ="h") note: 1 bit time = t osc (4/f osc ) = 1.2 m s (typ.) figure 6 grid and seg output timing (digital dimming mode) notes: 1. shown above is the timing in the digital dimming mode with the duty cycle of 2032/ 2048 at v park = "l". 2. the length of time that the grids and the segments are turned on is specified with respect to 11 bits of the ditigal dimming data. 3. 1 bit time = t osc (4/f osc ) = 1.2 m s (typ.) grid1 grid2 seg1-30 4096 bit times 1 frame 16 bit times 2032 bit times 6 bit times 2038 bit times 10 bit times
? semiconductor MSC1200-01/1200v-01 20/26 fedl1200v-03 grid1 grid2 seg1-30 4096 bit times 1 frame 2048 bit times max. 256 bit times figure 7 grid and seg output timing (analog dimming mode) notes: 1. shown above is the timing for the grid and seg drivers in the analog dimming mode at v park = "l". 2. 1 bit time = t osc (4/f osc ) = 1.2 m s (typ.)
? semiconductor MSC1200-01/1200v-01 21/26 fedl1200v-03 pla code table seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 seg 28 seg 29 seg 30 pin 24 pin 25 pin 26 pin 27 pin 28 pin 29 pin 30 pin 31 pin 32 pin 33 pin 34 pin 35 pin 36 pin 37 pin 38 pin 39 pin 40 pin 41 pin 42 pin 43 pin 44 pin 45 pin 46 pin 47 pin 48 pin 49 pin 50 pin 51 pin 52 pin 53 bit 1, 31 bit 2, 32 bit 3, 33 bit 4, 34 bit 5, 35 bit 6, 36 bit 7, 37 bit 8, 38 bit 9, 39 bit10, 40 bit11, 41 bit12, 42 bit13, 43 bit14, 44 bit15, 45 bit16, 46 bit17, 47 bit18, 48 bit19, 49 bit20, 50 bit21, 51 bit22, 52 bit23, 53 bit24, 54 bit25, 55 bit26, 56 bit27, 57 bit28, 58 bit29, 59 bit30, 60 seg1 pin name seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg16 pin name seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 bit 1, 31 output bit 2, 32 bit 3, 33 bit 4, 34 bit 5, 35 bit 6, 36 bit 7, 37 bit 8, 38 bit 9, 39 bit 10, 40 bit 16, 46 bit 17, 47 bit 18, 48 bit 19, 49 bit 20, 50 bit 21, 51 bit 22, 52 bit 23, 53 bit 24, 54 bit 25, 55 output seg11 seg12 seg13 seg14 seg15 seg26 seg27 seg28 seg29 seg30 bit 11, 41 bit 12, 42 bit 13, 43 bit 14, 44 bit 15, 45 bit 26, 56 bit 27, 57 bit 28, 58 bit 29, 59 bit 30, 60 pin name output
? semiconductor MSC1200-01/1200v-01 22/26 fedl1200v-03 v dim threshold dimming voltage vs. pwm duty cycle pulse step number pulse step number pwm duty cycle pulse count % % pulse count pwm duty cycle threshold voltage threshold voltage 12.5 11.7 10.9 10.2 9.38 8.98 8.59 8.20 7.81 7.42 7.03 6.64 6.25 5.86 5.47 5.08 4.69 4.49 4.30 4.10 3.91 3.71 3.52 3.32 3.13 2.93 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 256/2048 240/2048 224/2048 208/2048 192/2048 184/2048 176/2048 168/2048 160/2048 152/2048 144/2048 136/2048 128/2048 120/2048 112/2048 104/2048 96/2048 92/2048 88/2048 84/2048 80/2048 76/2048 72/2048 68/2048 64/2048 60/2048 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 56/2048 52/2048 48/2048 46/2048 44/2048 42/2048 40/2048 38/2048 36/2048 34/2048 32/2048 30/2048 28/2048 26/2048 24/2048 23/2048 22/2048 21/2048 20/2048 19/2048 18/2048 17/2048 16/2048 15/2048 14/2048 13/2048 2.73 2.54 2.34 2.25 2.15 2.05 1.95 1.86 1.76 1.66 1.56 1.46 1.37 1.27 1.17 1.12 1.07 1.03 0.98 0.93 0.88 0.83 0.78 0.73 0.68 0.63 0.000 4.200 4.130 4.070 4.000 3.930 3.890 3.850 3.810 3.770 3.725 3.680 3.625 3.580 3.525 3.460 3.400 3.340 3.305 3.270 3.240 3.200 3.160 3.120 3.080 3.040 2.93 3.000 v dd =12.8v 2.950 2.900 2.850 2.820 2.800 2.770 2.740 2.710 2.680 2.650 2.615 2.580 2.540 2.500 2.470 2.450 2.430 2.410 2.390 2.370 2.340 2.320 2.295 2.270 2.245 vref 0 note: a threshold voltage more than 5v cannot be set.
? semiconductor MSC1200-01/1200v-01 23/26 fedl1200v-03 application circuits (a) digital dimming 1/2-duty vf display tube driver seg1 seg30 g1 g2 v dd microcomputer small parking lamp sw luminance control resistor column5 column4 column3 column2 column1 row0 row1 column0 row2 row3 row4 gnd int cs datai/o clock osc1 osc0 v park v dim keyboard 2r r MSC1200-01
? semiconductor MSC1200-01/1200v-01 24/26 fedl1200v-03 (b) analog dimming 1/2-duty vf display tube driver seg1 seg30 g1 g2 v dd column5 column4 column3 column2 column1 row0 row1 column0 row2 row3 row4 gnd int cs datai/o clock osc1 microcomputer small parking lamp sw luminance control resistor osc0 v park dashboard lamp the setting voltage must not exceed 5v. v dim keyboard 2r r MSC1200-01 2r r
? semiconductor MSC1200-01/1200v-01 25/26 fedl1200v-03 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment package weight (g) oki electric industry co., ltd. rev. no./last revised epoxy resin 42 alloy solder plating ( 3 5 mm) 0.43 typ. 4/vov. 28, 1996 mirror finish qfp56-p-910-0.65-2k
? semiconductor MSC1200-01/1200v-01 26/26 fedl1200v-03 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 2000 oki electric industry co., ltd. printed in japan

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